Integrated circuits (IC's) often suffer from a lack of robustness with respect to ESD. As technology allows IC's to be scaled down into the submicron regime, various structures and processes, for example, in CMOS technology, such as thinner gate oxide, shorter channel length, shallower source/drain junction, LDD (Lightly Doped Drain) structures, and solicited diffusion, degrade the ESD robustness of IC's. (see e.g. C. Duvvury and A. Amerasekera, "ESD: A pervasive reliability concern for IC technologies," in Proc. of IEEE, vol. 81, no. 5. pp. 690-702, May 1993; and A. Amerasekera and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," 1994 EOS/ESD Symp. Proc., EOS-16, pp. 237-245).
To improve the ESD robustness of a submicron device, some submicron IC technologies offer an additional "ESD Implant" mask in processes to make a stronger device structure for an IC output buffer to protect against ESD damage. However, this results in increased IC fabrication costs.
Another approach to ESD protection in a CMOS output buffer is to provide one or more ESD protection elements between the CMOS output buffer and the output pad to improve the robustness of a submicron CMOS output buffer with respect to ESD.
In Y.-J. B. Liu and S. Cagnina, "Electrostatic discharge protection device for CMOS integrated circuit outputs," U.S. Pat. No. 4,734,752, 1988, a field-oxide (N-type) device is placed in parallel with the thin-oxide NMOS device of the CMOS output buffer from the output pad to VSS (ground) to improve the ESD protection capability of the CMOS output buffer. In T. C. Chan and D. S. Culver, "ESD protection circuit," U.S. Pat. No. 5,329,143, 1994, a lateral N-P-N bipolar transistor is placed in parallel with the thin-oxide NMOS device of the CMOS output buffer from the output pad to ground to improve the ESD protection capability of the CMOS output buffer. However, the turn-on voltages of a parasitic field-oxide device and parasitic lateral N-P-N bipolar transistor are generally higher than that of a short-channel thin-oxide NMOS device in the submicron CMOS output buffer. Thus, the thin-oxide NMOS device will be first turned on when the ESD stress occurs on this output pad. Thus, the improvement of ESD protection by adding the field-oxide device or lateral N-P-N bipolar transistor may be small.
In Scott et al., U.S. Pat. No. 5,019,888, 1991, the large-dimension output thin-oxide NMOS device is separated into many small-dimension NMOS devices in parallel with each other from the output pad to ground. There is a series resistance inserted from the drain of each small-dimension NMOS device to the output pad to improve its ESD robustness.
In G. N. Roberts, "Output ESD protection circuit," U.S. Pat. No. 5,218,222, 1993, a lateral N-P-N bipolar transistor is placed in parallel with the output NMOS device from the output node of the output buffer to ground, and a series resistance is inserted between the output pad and the output node of the output buffer, to improve ESD reliability of the output pad.
In K. F. Lee, A. Lee, M. L. Marmet, and K. W. Ouyang, "Electro-static discharge protection circuit with bimodal resistance characteristics," U.S. Pat. No. 5,270,565, 1993, a thick-oxide device is placed in parallel with the thin-oxide NMOS device in the CMOS output buffer from the output pad to VSS and the drain of the thin-oxide NMOS device in the CMOS output buffer is modified with a series N-well resistor to the output pad, to improve ESD protection capability of the CMOS output buffer.
In Scott et al., U.S. Pat. No. 5,019,888, 1991; G. N. Roberts, "Output ESD protection circuit," U.S. Pat. No. 5,218,222, 1993; and K. F. Lee, A. Lee, M. L. Marmet, and K. W. Ouyang, "Electro-static discharge protection circuit with bimodal resistance characteristics," U.S. Pat. No. 5,270,565, 1993, there are series resistors from the output node of the CMOS output buffer to the output pad. These series resistors could effectively improve ESD robustness of a submicron CMOS output buffer, but they limit the current driving/sinking capability of the CMOS output buffer. The timing for the output signal is also delayed by the series resistors. Thus, the output signal is also delayed by the series resistors. The output driving/sinking capability and output timing may also become outside of the design specifications. This limits the usefulness of an output buffer modified in this way for application in high-speed (minimum delay for input/output signal) and heavy-loading (output buffer of high-driving/sinking capability) CMOS IC's.
Since ESD voltages may have positive or negative polarities on a pin with respect to both VDD (high supply voltage) and VSS (low supply voltage or ground) pins, there are four different ESD-stress cases at an output pad of a CMOS output buffer:
(1) PS mode: ESD stress at an output pin with positive voltage polarity to VSS bus when VDD bus is floating; PA0 (2) NS mode: ESD stress at an output pin with negative voltage polarity to VSS bus when VDD bus is floating; PA0 (3) PD mode: ESD stress at an output pin with positive voltage polarity to VDD bus when VSS bus is floating and; PA0 (4) ND mode: ESD stress at an output pin with negative voltage polarity to VDD bus when VSS bus is floating.
These ESD voltages could damage both NMOS and PMOS devices in the output buffer of CMOS IC's.
The ESD failure threshold voltage of a pin is defined as the lowest ESD-sustaining voltage of the four-mode ESD stresses on the pin. For example, if an output pin can sustain up to 6 KV ESD voltage in PS-, NS-, and PD-mode ESD stresses but it can only sustain 1 KV ESD voltage in the ND-mode ESD stress, the ESD failure threshold voltage for this output pin is defined as 1 KV only. In the references cited above, the ESD protection is emphasized from the output pad to VSS (ground). The additional ESD protection elements are all placed from the output pad to ground in parallel with an output NMOS device. There is no additional ESD protection element arranged between the output pad and VDD. For ND-mode or PD-mode ESD stresses, the PMOS device of the CMOS output buffer (or the output device between VDD and output pad) is sensitive to ESD damage. The overall ESD failure threshold voltage may be not effectively improved. Thus, an effective ESD protection circuit for output buffer of advanced submicron CMOS IC's should provide strong ESD discharging paths from the output pad to both VSS and VDD buses.
FIG. 1 shows a schematic diagram of an ESD protection circuit. The circuit 40 is formed with protective circuitry 10, and output circuitry 30. The protective circuitry 10 also may include any type of two-terminal ESD protection device. Illustratively, NMOS 14 and PMOS 12 transistors are provided for ESD protection. However, as is apparent to one skilled in the art, the protective circuitry 10 may also be achieved using a variety of two-terminal devices. For example, an LVTSCR (Low Voltage Trigger SCR) may be used. Additionally, the protective circuitry 10 also includes a first parasitic diode D.sub.p (22) and a second parasitic diode D.sub.n (24).
The first parasitic diode D.sub.p is connected in parallel with the PMOS device with its anode connected to the output pad and its cathode connected to VDD. The D.sub.p diode is used to protect against PD mode ESD stress. A second parasitic diode D.sub.n is connected in parallel to the NMOS device with its anode connected to VSS and its cathode connected to the output pad. The diode D.sub.n protects against NS mode ESD stress. However, diodes fashioned in this method do not offer sufficient diode area for adequate ESD protection. Further, the costs of such a structure are typically quite high.
It is therefore an object of the present invention to overcome these deficiencies in the prior art. This is accomplished by incorporating an ESD element in a modified seal ring structure. This allows such ESD element to share most of the ESD current during an event to improve ESD protection. In addition, the structure allows the size of the primary ESD circuitry to be reduced.